Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same

ABSTRACT

An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line.

RELATED APPLICATION

This application is a continuation application of U.S. patent application Ser. No. 12/467,331, filed May 18, 2009, entitled “Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same,” which is a divisional application of U.S. patent application Ser. No. 11/821,848, filed Jun. 26, 2007, entitled “Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same,” which claims priority to U.S. Provisional Application No. 60/830,084, entitled “Integrated Circuit Having Memory Array having a Segmented Bit Line Architecture, and Method of Controlling and/or Operating Same”, filed Jul. 11, 2006, each of which is incorporated by reference herein in its entirety.

BACKGROUND

In one aspect, the present inventions described and illustrated herein relate to an integrated circuit device having a memory cell array including a plurality of rows and columns, and techniques for controlling and/or operating such a device. More particularly, in one aspect, the present inventions relate to an integrated circuit having memory cell array including a plurality of bit lines and a plurality of bit line segments, wherein a plurality of bit line segments are associated with each bit line, and wherein each bit line segment includes a plurality of memory cells (for example, memory cells having an electrically floating body in which a charge is stored) associated therewith and connected thereto; isolation circuits selectively and responsively couple an associated bit line segment to an associated bit line.

Briefly, with reference to FIG. 1, memory cell array 10 typically includes a plurality of memory cells 12 arranged in a matrix of rows and columns. A row address decoder enables one or more rows to be read by sensing circuitry (for example, a plurality of sense amplifiers). A column decoder, in response to an address, selects one or more of the outputs of the data sensing circuitry.

One type of dynamic random access memory cell is based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662). In this regard, the memory cell may consist of a partially depleted (PD) or a fully depleted (FD) SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of cell is determined by the concentration of charge in the body of the transistor.

With reference to FIGS. 2A, 2B, 2C and 2D, memory cell array 10 may include a plurality of memory cells 12, each consisting of transistor 14 having gate 16, an electrically floating body region 18, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material) or non-conductive region (for example, in bulk-type material). The insulation or non-conductive region may be disposed on substrate 26.

Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, and/or a selected bit line(s) 32. The source line (30) is a common node in a typical implementation though it could be similarly decoded. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.

As mentioned above, memory cell 12 of memory cell array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18 of, for example, N-channel transistors. (See, FIGS. 3A and 3B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or “1” data state. (See, FIG. 3A). Emitting or ejecting majority carriers 34 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or “0” data state. (See, FIG. 3B).

Notably, an advantage of the floating body memory cell compared to a more traditional DRAM cell (i.e., one transistor and one capacitor) is that the floating body memory cell does not require an associated capacitor to store charge. This tends to reduce process complexity and provide a smaller memory cell footprint. In this way, the cost of a memory cell array implementing such memory cells is less than conventional memory cell arrays.

Another significant concern in memory cell arrays is power consumption. The need for products with reduced power consumption is particularly acute due to proliferation of battery powered products. With the floating body memory, one source of power consumption is the power consumed during refresh operations. A refresh operation involves reading the state of a cell and re-writing that cell to the state that was read. This may be necessary as a result of gradual loss of charge over time in the floating body. The rate of charge loss increases in a floating body array when disturb voltages are applied to the nodes of a given cell. These disturb voltages occur in an array when reads and writes are made to rows in a shared array. The unselected row remains with its gate off, but its drain nodes are “exposed” to changing voltages due to the voltages applied to the shared bit line.

Notably, the above mentioned disturb voltage tends to reduce the refresh interval necessary to maintain stored data and thus, increase the power consumption required to maintain stored data.

SUMMARY OF INVENTIONS

There are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

In a first principle aspect, certain of the present inventions are directed to an integrated circuit device (for example, logic device or discrete memory device) comprising a memory cell array including (1) a plurality of bit lines, (2) a plurality of bit line segments, wherein at least two bit line segments are associated with each bit line and wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line, (3) a plurality of word lines, and (4) a plurality of memory cells, wherein each memory cell stores at least two data states and includes a transistor. Each transistor of each memory cell includes a first region connected to an associated bit line segment, a second region, a body region disposed between the first region and the second region, and a gate disposed over the body region and coupled to an associated word line. The integrated circuit device includes a first group of memory cells is coupled to a first bit line via a first bit line segment, a second group of memory cells is coupled to the first bit line via a second bit line segment, a third group of memory cells is coupled to a second bit line via a third bit line segment, and a fourth group of memory cells is coupled to the second bit line via a fourth bit line segment. The integrated circuit device of certain aspects of the inventions also includes first circuitry, coupled to the first and second bit lines, to sense the data state stored in the memory cells of the first, second, third and fourth groups of memory cells.

In one embodiment, the integrated circuit device may include a plurality of isolation circuits, wherein each isolation circuit is associated with a bit line segment and wherein each isolation circuit is disposed between the associated bit line segment and the associated bit line thereof. The isolation circuit responsively connects the associated bit line segment to or disconnects the associated bit line segment from the associated bit line.

In one embodiment, each isolation circuit includes a first transistor (P-type or an N-type transistor) comprising: (i) a first region connected to the associated bit line, (ii) a second region connected to the associated bit line segment, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal. In another embodiment, each isolation circuit further includes a second transistor (P-type or an N-type transistor) comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.

In another embodiment, each isolation circuit includes a plurality of transistors including a first transistor and a second transistor, wherein the first and second transistors are arranged in a CMOS configuration. The isolation circuit may further include a third transistor comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.

In yet another embodiment of this aspect of the inventions, the integrated circuit device further includes a plurality of isolation circuits, wherein each isolation circuit is associated with a bit line segment and wherein each isolation circuit is disposed between the associated bit line segment and the associated bit line thereof. The plurality of isolation circuit includes first isolation circuit is disposed between the first bit line segment and the first bit line, a second isolation circuit is disposed between the second bit line segment and the first bit line. The first and second isolation circuits each include a transistor comprising: (i) a first region connected to the first bit line, (ii) a second region connected to the associated bit line segment, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal, wherein the transistors of the first and second isolation circuits share the first region. In one embodiment, the transistors of the first and second isolation circuits include P-type transistors or N-type transistors. The first and second isolation circuits may each further include a clamp transistor comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.

In one embodiment, the number of memory cells in each of the first, second, third and fourth groups of memory cells may be equal to or greater than two. In another embodiment, the number of memory cells in each of the first, second, third and fourth groups of memory cells is equal to or greater than four.

In another principle aspect, certain of the present inventions are directed to an integrated circuit device (for example, logic device or discrete memory device) comprising a memory cell array, including a plurality of bit lines, a plurality of bit line segments, wherein at least two bit line segments are associated with each bit line and wherein each bit line segment is selectively and responsively coupled to or decoupled from associated bit line, a plurality of word lines, and a plurality of isolation circuits, wherein an isolation circuit is disposed between an associated bit line segment and associated bit line thereof, and wherein the isolation circuit responsively connects the associated bit line segment to or disconnects the associated bit line segment from the associated bit line. In this aspect, a plurality of memory cells are arranged in groups wherein each group of memory cells is connected to an associated bit line segment, and wherein each memory cell stores at least two data states which are representative of an amount of charge in the body region, each memory cell includes a transistor. Each transistor includes a first region connected to an associated bit line segment, a second region, a body region disposed between the first region and the second region, wherein the body region is electrically floating, and a gate disposed over the body region and coupled to an associated word line. The integrated circuit device of this aspect of the inventions also includes first circuitry, coupled to bit lines, to sense the data state stored in the memory cells.

In one embodiment, each isolation circuit includes a first transistor (a P-type or an N-type transistor) comprising: (i) a first region connected to the associated bit line, (ii) a second region connected to the associated bit line segment, (iii) a body region disposed between the first region and the second region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region and configured to receive a control signal. Each isolation circuit may further include a second transistor (a P-type or an N-type transistor) comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region and configured to receive a control signal.

In another embodiment, each isolation circuit may include a plurality of transistors including a first transistor and a second transistor which are arranged in a CMOS configuration. The isolation circuits of this embodiment may each also include a third transistor comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, wherein the body region is electrically floating, and (iv) a gate disposed over the body region and configured to receive a control signal.

In one embodiment, the number of memory cells in each group of memory cells may be equal to or greater than two. In another embodiment, the number of memory cells in each of group of memory cells is equal to or greater than four. Indeed, in yet another embodiment, the number of memory cells in each of group of memory cells may be odd or even.

In another principle aspect, certain of the present inventions are directed to an integrated circuit device (for example, logic device or discrete memory device) comprising a memory cell array including a plurality of bit lines, a plurality of bit line segments, wherein at least two bit line segments are associated with each bit line and wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line, a plurality of word lines and a plurality of isolation circuits, wherein an isolation circuit is disposed between each bit line segment and its associated bit line, and wherein the isolation circuit responsively connects the associated bit line segment to or disconnects the associated bit line segment from the associated bit line. The memory cell array also includes a plurality of memory cells, wherein each is connected to an associated bit line segment, stores at least two data state and consists essentially of a transistor, wherein each transistor includes a first region connected to an associated bit line segment, a second region, a body region disposed between the first region and the second region, wherein the body region is electrically floating and a gate disposed over the body region and coupled to an associated word line. A first group of memory cells is coupled to a first bit line via a first bit line segment. A second group of memory cells is coupled to the first bit line via a second bit line segment. A third group of memory cells is coupled to a second bit line via a third bit line segment. A fourth group of memory cells is coupled to the second bit line via a fourth bit line segment. The integrated circuit device of this aspect of the inventions further first circuitry, coupled to the first and second bit lines, to sense the data state stored in the memory cells of the first, second, third and fourth groups.

In one embodiment, the integrated circuit device may include a plurality of isolation circuits, wherein each isolation circuit is associated with a bit line segment and wherein each isolation circuit is disposed between the associated bit line segment and the associated bit line thereof. The isolation circuit responsively connects the associated bit line segment to or disconnects the associated bit line segment from the associated bit line.

In one embodiment, each isolation circuit includes a first transistor (P-type or an N-type transistor) comprising: (i) a first region connected to the associated bit line, (ii) a second region connected to the associated bit line segment, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal. In another embodiment, each isolation circuit further includes a second transistor (P-type or an N-type transistor) comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.

In another embodiment, each isolation circuit includes a plurality of transistors including a first transistor and a second transistor, wherein the first and second transistors are arranged in a CMOS configuration. The isolation circuit may further include a third transistor comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.

In yet another embodiment of this aspect of the inventions, the integrated circuit device further includes a plurality of isolation circuits, wherein each isolation circuit is associated with a bit line segment and wherein each isolation circuit is disposed between the associated bit line segment and the associated bit line thereof. The plurality of isolation circuit includes first isolation circuit is disposed between the first bit line segment and the first bit line, a second isolation circuit is disposed between the second bit line segment and the first bit line. The first and second isolation circuits each include a transistor comprising: (i) a first region connected to the first bit line, (ii) a second region connected to the associated bit line segment, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal, wherein the transistors of the first and second isolation circuits share the first region. In one embodiment, the transistors of the first and second isolation circuits include P-type transistors or N-type transistors. The first and second isolation circuits may each further include a clamp transistor comprising: (i) a first region connected to the associated bit line segment, (ii) a second region connected to a predetermined voltage, (iii) a body region disposed between the first region and the second region, and (iv) a gate disposed over the body region and configured to receive a control signal.

In one embodiment, the number of memory cells in each of the first, second, third and fourth groups of memory cells may be equal to or greater than two. In another embodiment, the number of memory cells in each of the first, second, third and fourth groups of memory cells is equal to or greater than four.

Again, there are many inventions, and aspects of the inventions, described and illustrated herein. This Summary of the Inventions is not exhaustive of the scope of the present inventions. Indeed, this Summary of the Inventions may not be reflective of or correlate to the inventions protected in this and/or in continuation/divisional applications hereof.

Moreover, this Summary of the Inventions is not intended to be limiting of the inventions or the claims (whether the currently presented claims or claims of a divisional/continuation application) and should not be interpreted in that manner. While certain embodiments have been described and/or outlined in this Summary of the Inventions, it should be understood that the present inventions are not limited to such embodiments, description and/or outline, nor are the claims limited in such a manner (which should also not be interpreted as being limited by the Summary of the Inventions).

Indeed, many other aspects, inventions and embodiments, which may be different from and/or similar to, the aspects, inventions and embodiments presented in this Summary, will be apparent from the description, illustrations and claims, which follow. In addition, although various features, attributes and advantages have been described in this Summary of the Inventions and/or are apparent in light thereof, it should be understood that such features, attributes and advantages are not required whether in one, some or all of the embodiments of the present inventions and, indeed, need not be present in any of the embodiments of the present inventions.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present inventions and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present inventions.

Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those permutations and combinations will not be discussed separately herein.

FIG. 1 is a schematic block diagram illustration of a conventional memory cell array having a plurality of memory cells arranged in an array of a plurality of rows and columns, in conjunction with row and column address decoders, word line drivers and data sense circuitry;

FIG. 2A is a schematic representation of a portion of a prior art memory cell array including a plurality of memory cells wherein each memory cell includes one electrically floating body transistor;

FIG. 2B is a three dimensional view of an exemplary prior art memory cell comprised of one electrically floating body transistor (PD-SOI NMOS);

FIG. 2C is a cross-sectional view of the memory cell of FIG. 2B, cross-sectioned along line C-C′;

FIG. 2D is a plan view layout (not drawn to scale) of a portion of the memory cell array of FIG. 2A;

FIGS. 3A and 3B are exemplary schematic illustrations of the charge relationship, for a given data state, of a prior art memory cell comprised of an electrically floating body transistor (N-channel type transistor);

FIGS. 4A and 4B are schematic block diagram illustrations of a portion of an exemplary memory cell array including exemplary segmented bit line architectures in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein each isolation circuit in this exemplary embodiment is an electrically floating body transistor (N-channel type transistors);

FIG. 4C is a schematic block diagram illustration of a portion of an exemplary memory cell array including an exemplary segmented bit line architecture in conjunction with isolation circuits and peripheral circuitry (i.e., reference generator circuitry and data sense/write circuitry), according to certain aspects of the present inventions, wherein the adjacent bit lines are connected to different data sense/write circuitry;

FIG. 4D is an exemplary plan view layout (not drawn to scale) of a portion of the memory cell array of FIGS. 4A and 4B illustrating the segmented bit line architecture and isolation circuit, according to certain aspects of the present inventions;

FIG. 4E is a schematic block diagram illustration of a portion of an exemplary memory cell array including exemplary segmented bit line architectures in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein each isolation circuit in this exemplary embodiment is an electrically floating body transistor (N-channel type transistors);

FIG. 4F is an exemplary plan view layout (not drawn to scale) of a portion of the memory cell array of FIG. 4E illustrating the segmented bit line architecture and isolation circuit, according to certain aspects of the present inventions;

FIGS. 5A-5C are schematic block diagram illustrations of a portion of a exemplary memory cell array including an exemplary segmented bit line architecture in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein each isolation circuit in this exemplary embodiment is a P-channel type electrically floating body transistor (FIGS. 5A and 5B) or an N-channel type electrically floating body transistor (FIG. 5C);

FIG. 5D is a plan view an exemplary layout (not drawn to scale) of a portion of the memory cell array of FIG. 5A illustrating the segmented bit line architecture and isolation circuit, according to certain aspects of the present inventions;

FIG. 6A is a schematic block diagram illustration of a portion of an exemplary memory cell array including an exemplary segmented bit line architecture in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein each isolation circuit includes two isolation transistors arranged in a CMOS circuit or configuration;

FIG. 6B is a plan view an exemplary layout (not drawn to scale) of a portion of the memory cell array of FIG. 6A illustrating the segmented bit line architecture and isolation circuit, according to certain aspects of the present inventions;

FIGS. 7A-7C are schematic block diagram illustrations of a portion of an exemplary memory cell array including an exemplary segmented bit line architecture in conjunction with isolation circuits and certain peripheral circuitry, according to certain aspects of the present inventions, wherein adjacent bit line segment-isolation circuit blocks are configured in a mirrored arrangement;

FIG. 7D is a plan view an exemplary layout (not drawn to scale) of a portion of the memory cell array of FIG. 7A illustrating the segmented bit line architecture and isolation circuit, according to certain aspects of the present inventions;

FIGS. 8A-8D are schematic block diagram illustrations of a portion of an exemplary memory cell array including a plurality of exemplary segmented bit line architectures in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein each isolation circuit includes an isolation transistor and a clamp transistor;

FIG. 8E is a plan view an exemplary layout (not drawn to scale) of a portion of the memory cell array of FIG. 8A illustrating the segmented bit line architecture and isolation circuit, according to certain aspects of the present inventions;

FIGS. 9A and 9B are schematic block diagram illustrations of a portion of an exemplary memory cell array including exemplary segmented bit line architectures in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein each bit line segment includes an odd number of memory cells connected thereto;

FIGS. 10A-10C are schematic block diagram illustrations of an exemplary devices in which the present inventions may be implemented wherein FIGS. 10A and 10C are logic devices (having logic circuitry and resident memory) and FIG. 10B is a memory device (including primarily one or more memory arrays), according to certain aspects of the present inventions;

FIGS. 11A-11C are schematic representations of exemplary memory cell array(s), including a plurality of memory cells (for example, electrically floating transistors) in conjunction with data sense circuitry, according to various embodiments of the present inventions;

FIGS. 12A and 12B is a schematic block diagram illustration of a portion of an exemplary memory cell array including an exemplary segmented bit line architecture in conjunction with isolation circuits, according to certain aspects of the present inventions, wherein the memory cells may be any memory cell technology;

FIGS. 13A and 13B are exemplary schematic block diagram representations of memory cell selection circuitry, in conjunction with a row decoder, according to various embodiments of the present inventions; and

FIG. 13C is a schematic block diagram representation of isolation circuitry drivers, according to one exemplary embodiment of the present inventions.

Again, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For the sake of brevity, many of those combinations and permutations are not discussed separately herein.

DETAILED DESCRIPTION

There are many inventions described and illustrated herein. In one aspect, the present inventions are directed to an architecture, a configuration and/or a layout of a semiconductor memory cell array having a plurality of memory cells, arranged in a plurality of rows and columns. The memory cell array includes a plurality of bit lines, wherein each bit line is coupled to circuitry to read data from or write data into memory cells associated with the bit line. The memory cell array of the present inventions further includes a plurality of bit line segments coupled to each bit line, wherein each bit line segment is selectively and responsively coupled to its associated bit line via an associated isolation circuit. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory). In one embodiment of this aspect of the present inventions, each memory cell includes at least one electrically floating body transistor.

In another aspect, the present inventions are directed to techniques to control, read from and/or write data into one or more memory cells of the memory cell array. In this regard, in one embodiment, an integrated circuit device may include circuitry to implement the control, read and/or write operations/techniques with respect to the memory cell array having a plurality of bit line segments responsively coupled to each of the bit lines via an associated isolation circuit. In one embodiment of the present inventions, each memory cell includes at least one electrically floating body transistor.

With reference to FIG. 4A, integrated circuit device 100, according to one embodiment of the present inventions, includes memory cell array 102 having a plurality of memory cells 12, each including electrically floating body transistor 14. Each memory cell 12 is connected to an associated word line 28 (via the gate of transistor 14) and an associated bit line 32 (via the drain of transistor 14). In this embodiment, a plurality of memory cells 12 are connected to an associated bit line segment 32 x via an associated bit line segment 32 x _(n) and an associated isolation circuit 104 x _(n). For example, the drain regions of adjacent transistors 14 a ₁-14 a ₄ of adjacent memory cells 12 a ₁-12 a ₄, respectively, are connected to an associated bit line segment 32 a ₁. The bit line segment 32 a ₁ is connected to isolation circuit 104 a ₁ which responsively connects bit line segment 32 a ₁ to bit line 32 a. Similarly, the drain regions of adjacent transistors 14 a ₅-14 a ₈ of adjacent memory cells 12 a ₅-12 a ₈, respectively, are connected to bit line 32 a via bit line segment 32 a ₂ and isolation circuit 104 a ₂. Likewise, bit line segment 32 a ₂ is connected to isolation circuit 104 a ₂ which responsively connects bit line segment 32 a ₂ to bit line 32 a.

Notably, the source regions of transistors 14 of memory cells 12 may be connected to a common signal line that may be routed parallel to word lines 28. A predetermined voltage (for example, a ground, common potential or decoded signal) may be applied to the common signal line.

In this exemplary embodiment, isolation circuit 104 x _(n) includes isolation transistor 106 x ₄ having a first region (for example, source region) connected to bit line segment 32 x _(n), and a second region (for example, drain region) connected to bit line 32 x. As such, in this embodiment, an isolation enable signal is applied to the gate of isolation transistor 106 x _(n), via isolation select line 108 x _(n), to connect bit line segment 32 x _(n), to associated bit line 32 x. In response to the isolation enable signal, the transistor 106 x _(n) connects bit line segment 32 x _(n) to associated bit line 32 x. For example, in response to an isolation enable signal applied to isolation select line 108 a, the source region of isolation transistor 106 connects bit line segment 32 a ₁ to bit line 32 a.

Notably, in this exemplary embodiment, four adjacent memory cells 12 are connected to an associated bit line segment 32 x _(n). The present inventions may, however, be implemented with any number of memory cells 12, whether odd or even, connected to an associated bit line segment 32 x _(n). Indeed, any number of memory cells 12, whether odd or even, is intended to fall within the scope of the present inventions.

The integrated circuit device 100 further includes memory cell selection circuitry 110 and reading and programming circuitry 112. Briefly, memory cell selection circuitry 110 selects or enables one or more memory cells 12 to facilitate reading data therefrom and/or writing data thereto by applying a control signal, for example, on one or more word line 28 and isolation select lines 108. The memory cell selection circuitry 110 may generate such control signals using address data, for example, row address data. Indeed, memory cell selection circuitry 110 may include a conventional word line decoder and/or driver. There are many different control/selection techniques (and circuitry therefor) to implement the memory cell selection technique. Such techniques, and circuitry therefor, are well known to those skilled in the art. All memory cell control/selection techniques, and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions.

Notably, memory cell selection circuitry 110 may generate the isolation enable signal(s) using the row addresses and appropriate addressing decoding architecture (which may be a subset of the pre-existing decoding architecture). In addition thereto, or in lieu thereof, memory cell selection circuitry 110 may employ the control signals applied on the associated word line 28 in conjunction with appropriate logic (for example, an n-input OR gate wherein the “n” inputs are connected to word lines 28 which are connected to memory cells 12 which are associated with bit line segment 32 x _(n); in this way, if any of the associated word lines 28 are enabled, the OR gate connected to receive those word lines 28 generates an active high for the associated isolation enable signal (See, for example, FIG. 13C)). Indeed, memory cell selection circuitry 110 may employ any control/selection techniques, and circuitry therefor, whether now known or later developed, to enable and/or control the isolation circuits 104; all such techniques and circuitry are intended to fall within the scope of the present inventions.

Alternatively, during “inactive” memory cycles, the “default” condition may include bit line segments 32 x _(n) connected to their respective associated bit lines 32 x. Under these circumstances, during an active cycle, the decoded or selected bit line segment(s) may remain connected to the associated bit line and all unaddressed or unselected segments 32 may be isolated from the associated bit lines via associated isolation circuits 104. As such, in this embodiment, the bit line segments are connected to their respective associated until the associated isolation circuits are disabled (or enabled depending on the type of isolation circuit employed) thereby disconnecting unselected bit line segments form their associated bit line.

As mentioned above, reading and programming circuitry 112 reads data from and writes data to selected memory cells 12. With reference to FIG. 4B, in one embodiment, the reading and programming circuitry 112 includes a plurality of data sense/write circuitry 114 having data sense amplifiers. Each data sense/write circuitry 114 receives at least one bit line 32 and an output of reference generator circuitry 116 (for example, a current or voltage reference signal). In one embodiment, data sense/write circuitry 114 a-x includes a data sense amplifier (for example, a cross-coupled sense amplifier as described and illustrated in the Non-Provisional U.S. patent application Ser. No. 11/299,590, filed by Waller and Carman, on Dec. 12, 2005, and entitled “Sense Amplifier Circuitry and Architecture to Write Data into and/or Read Data from Memory Cells” (U.S. Patent Application Publication No. US 2006 0126374), the application being incorporated herein by reference in its entirety) to sense the data state stored in memory cell 12 and/or write-back data into memory cell 12. The data sense amplifier may employ voltage and/or current sensing circuitry and/or techniques. In the context of current sensing, a current sense amplifier may compare the current from the selected memory cell to a reference current, for example, the current of one or more reference cells. From that comparison, the circuitry may be determined whether memory cell 12 contained a logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 28 contained within body region 18).

The present inventions may employ any type or form of data sense/write circuitry 114 to read the data stored in memory cells 12. For example, the data sense/write circuitry 114 may implement one or more sense amplifiers, using voltage or current sensing techniques, to sense the data state stored in memory cell 12.

Moreover, the present inventions may employ any architecture or layout and/or technique of sensing data from and/or writing data into memory cells 12. For example, reading and programming circuitry 112 may employ the architectures, circuitry and techniques described and illustrated in U.S. Non-Provisional patent application Ser. No. 11/787,718, filed by Popoff, on Apr. 17, 2007, and entitled “Semiconductor Memory Array Architecture, and Method of Controlling Same”, the application being incorporated herein by reference in its entirety. Briefly, with reference to FIG. 4C, in one embodiment, reading and programming circuitry 112 includes data sense/write circuitry 114 a coupled to bit lines 32 a and 32 c, and data sense/write circuitry 114 b coupled to bit lines 32 b and 32 d. In a read or write operation, one of the bit lines (i.e., the active bit line) is selectively connected to the data sense and/or write circuitry in order to sense the data state in a memory cell 12 and/or write a data state into a memory cell 12 which is associated with the selected bit line. For example, during a read or write operation, one of the bit lines 32 a and 32 c is connected to the sense circuitry in data sense/write circuitry 114 a. Similarly, one of the bit lines 32 b and 32 d is connected to the sense circuitry in data sense/write circuitry 114 b.

In one embodiment, the active bit line is selected by memory cell selection circuitry 110 using, for example, one or more bits of the row address (for example, the MSB or LSB). Notably, the other bit line is disconnected from the sensing circuitry of data sense/write circuitry 114. Again, the architectures, circuitry and/or techniques described and illustrated in U.S. Non-Provisional patent application Ser. No. 11/787,718 are incorporated by reference herein.

Notably, with reference to FIGS. 4A-4C, integrated circuit device 100 may also include reference generator circuitry 116. The reference generator circuitry 116 generates a reference signal (for example, a voltage and/or current reference signal) which is provided to reading and programming circuitry 112 via signal line 118. The reading and programming circuitry 112, and, in particular, data sense/write circuitry 108 employs the reference signal to determine the data state of the selected memory cell 12 during, for example, a read operation.

With continued reference to FIGS. 4A and 4B, in a read operation, memory cell selection circuitry 110, in response to an address signal designating memory cells 12 connected to, for example, word line 28 d, applies a control signal on word line 28 d and isolation select line 108 a. In response, isolation circuit 104 a ₁ couples bit line segment 32 a ₁ to bit line 32 a. In this way, the data sensing circuitry (for example, a cross-coupled sense amplifier) of reading and programming circuitry 112 may read the data state of memory cell 12 a ₄.

Similarly, isolation circuit 104 b ₁, in response to a isolation select signal applied on isolation select line 108 a, couples bit line segment 32 b ₁ to bit line 32 b. As such, the data state of memory cell 12 b ₄ may be read by the data sensing circuitry of reading and programming circuitry 112. As mentioned above, in one embodiment, during a read operation, the data sensing circuitry in reading and programming circuitry 112 compares a signal from the selected memory cells 12 (in this example, memory cells 12 a ₄ and 12 b ₄) to a reference signal from reference generator circuitry 116 to determine the data state stored in the selected memory cells 12.

Notably, during the exemplary read operation, isolation circuit 104 a ₂ and isolation circuit 104 b ₂ isolate memory cells 12 which are associated with or connected to bit line segments 32 a ₂ and 32 b ₂ (i.e., memory cells 12 a ₅-12 a ₈ and 12 b ₅-12 b ₈, respectively). That is, transistors 14 of memory cells 12 which are connected to the other bit line segments 32 x _(n) associated with bit lines 32 a and 32 b are “isolated” during the read or write operations. Thus, when a drain voltage is passed through isolation transistor 106 associated with the selected memory cell 12 of the associated bit line segments 32 x _(n), the voltage may adversely impact the other cells of that bit line segment; the other memory cells 12 in memory cell array 102 are isolated. Accordingly, such memory cells are less susceptible to voltage/current disturbance on bit line 32 during the read operation of memory cells 12 connected to other bit line segments 32 x _(n) (in this example, bit line segments 32 a ₁ and 32 b ₁). Indeed, the present inventions may facilitate implementing significant burst read and write operations where the memory cells isolated from bit lines 32, via isolation circuit 104 x _(n), may be read in a burst read manner (for example, by sequentially addressing those word lines 28 which are associated with a given bit line segment 32).

In a write operation, in response to an address signal designating memory cells 12 connected to, for example, word line 28 e, memory cell selection circuitry 110 applies a control signal on word line 28 e and isolation select line 108 b. In response, isolation circuit 104 a ₂ couples bit line segment 32 a ₂ to bit line 32 a. Similarly, isolation circuit 104 b ₂, in response to an isolation select signal applied on isolation select line 108 b, couples bit line segment 32 b ₂ to bit line 32 b. In this way, the data writing circuitry of reading and programming circuitry 112 may write (or refresh) the data state of memory cells 12 a ₅ and 12 b ₅.

During the exemplary write operation, isolation circuits 106 a ₁ and 106 b ₁ isolate memory cells 12 which are connected to bit line segments 32 a ₁ and 32 b ₁ (i.e., memory cells 12 a ₁-12 a ₄ and 12 b ₁-12 b ₄, respectively). Accordingly, such memory cells are less susceptible to voltage/current disturbance on bit line 32 during the write operation of memory cells 12 connected to other bit line segments 32 x _(n) (in this example, bit line segments 32 a ₂ and 32 b ₂). Moreover, as noted above in the context of a read operation, the present inventions may facilitate implementing significant burst write operations where the memory cells isolated from bit lines 32, via isolation circuit 104 x _(n), may be written in a burst write manner (for example, by sequentially addressing those word lines 28 which are associated with a given bit line segment 32).

Notably, the discussion above with respect to FIGS. 4A-4C is applicable to the embodiment illustrated in FIG. 4E wherein the source lines 32 are, among other things, routed parallel to word lines 28. For the sake of brevity, such discussions will not be repeated.

As discussed above, in one embodiment, the present inventions may include memory cells 12 having electrically floating body transistor 14, as described above. The memory cells 12 may include electrically floating body transistor 14 that are N-channel type transistor (see, FIGS. 4A-4C, 4E and 5A) or P-channel type transistors (see, FIGS. 5B and 5C). In addition, isolation circuit 104 a, may include N-channel type transistor(s) (see, FIGS. 4A-4C and 4E) or P-channel type transistors (see, FIGS. 5A and 5B). Where isolation circuit 104 includes a P-channel type transistor(s), a more efficient positive voltage transfer may be obtained between (i) bit line segment 32 x _(n) and its associated bit line 32 (during a read operation) and (ii) bit line 32 and its associated bit line segment 32 x _(n) (during a write operation). Moreover, where isolation circuit 104 includes a N-channel type transistor(s) and the memory cells 12 include P-channel type transistor 14 (see, for example, FIG. 5C), a more efficient voltage transfer may be obtained between (i) bit line segment 32 x _(n) and its associated bit line 32 (during a read operation) and (ii) bit line 32 and its associated bit line segment 32 x _(n) (during a write operation). Notably, however, it may be advantageous to employ the same type of transistors for the memory cells and isolation circuit 104 a ₁. In this way, a more compact design may be achieved, for example, where memory array 10 is formed in bulk material/substrate.

In another embodiment, isolation circuit 104 may include a plurality of transistors 106 x _(nm) and 106 x _(nm+1). For example, with reference to FIG. 6A, isolation circuit 104 a ₁ includes isolation transistors 106 a ₁₁ and 106 a ₁₂ and isolation circuit 104 a ₂ includes isolation transistors 106 a ₂₁ and 106 a ₂₂. In this embodiment, isolation transistors 106 a ₁₁ and 106 a ₁₂ and isolation transistors 106 a ₂₁ and 106 a ₂₂ each form a CMOS arrangement/circuit. As such, in operation, in response to an address signal designating memory cells 12 a ₁ connected to, for example, word line 28 a, memory cell selection circuitry 110 applies a control signal on word line 28 a and isolation select line 108 a ₁ and 108 a ₂. In response, isolation circuit 104 a ₁ couples bit line segment 32 a ₁ to bit line 32 a. The isolation circuit 104 a ₂ is not enabled and, as such, maintains bit line segment 32 a ₂ disconnected from bit line 32 a. In this way, memory cells 12 a ₅-12 b ₈ are isolated from bit line 32 a during the read or write operations and, when a drain voltage is passed through isolation transistor 104 a ₁₁ and 104 a ₁₂, the voltage does not adversely impact the memory cells associated with the bit line segments associated with bit line 32 a. Accordingly, such memory cells are less susceptible to voltage/current disturbance on bit line 32 b during the read operation of memory cells 12 a ₁. Indeed, as noted above, the present inventions may facilitate implementing significant burst read and write operations where the memory cells isolated from bit lines 32, via isolation circuit 104 x _(n), may be read in a burst read manner.

Implementing a CMOS isolation circuit may enhance or improve the charge transfer from bit line 32 x to an associated segmented bit line 32 x _(n), (and/or vice versa). In addition to providing a more complete charge transfer from bit line 32 to the associated segmented bit line 32 x _(n), employing a CMOS isolation circuit may also enhance the access times of the read and write operations. Notably, although there may be certain inefficiency in the size and layout of memory cell array 102, such inefficiency may be mitigated by increasing the number of memory cells 12 which are associated with a given bit line segment 32 x _(n) and/or increasing the number of bit line segments 32 x _(n) associated with each bit line 32.

In another embodiment, isolation circuits 104 may be located adjacent each other, in a mirror layout, to improve array efficiency. In this regard, isolation transistors 106 x _(n) of isolation circuits 104 may be juxtaposed so that the one or more regions of isolation transistors 106 x _(n) are “shared” or are a common region. For example, with reference to FIGS. 7A and 7B, in one exemplary embodiment, isolation transistor 106 a ₁ and isolation transistor 106 a ₂ share a drain region which may reduce the area of the isolation circuits 104 and thereby improve the efficiency of memory cell array 102.

With reference to FIG. 7C, in another example, isolation circuits 104 having a CMOS architecture may also include a mirror layout, to improve array efficiency. In this regard, the PMOS or NMOS type isolation transistors 106 x _(n) of adjacent isolation circuits 104 may be juxtaposed so that the one or more regions of isolation transistors 106 x _(n) are “shared” or are a common region. In the illustrated embodiment, PMOS-type isolation transistor 106 a ₁₂ and PMOS-type isolation transistor 106 a ₂₂ may share a drain region. In this way, the area occupied by isolation circuits 104 a ₁ and 104 a ₂ may be reduced which may improve the efficiency of memory cell array 102.

In another embodiment, isolation circuits 104 include two or more transistors including an isolation transistor and a clamp transistor. With reference to FIG. 8A, in one embodiment, isolation circuit 104 x includes isolation transistor 106 x _(nm) and clamp transistor 106 x _(nm+1). For example, isolation circuit 104 a ₁ includes isolation transistor 106 a ₁₁ and clamp transistor 106 a ₁₂. In this embodiment, isolation transistor 106 x _(nm) (for example, isolation transistor 106 a ₁₁) selectively and responsively connects/isolates associated bit line segment 32 x _(n) (for example, bit line segment 32 a ₁) to the associated bit line 32 x (for example, bit line 32 a). The clamp transistor 106 x _(nm+1) is employed to hold or maintain associated bit line segment 32 x _(n) at a predetermined voltage. In this illustrative embodiment, the predetermined voltage may be a fixed voltage, such as, for example, ground, common or 0 Volts. In this way, the voltage on bit line segment 32 x _(n) is not “floating” but may be maintained at a predetermined and/or fixed voltage.

With continued reference to FIG. 8A, in operation, in response to an address signal designating memory cells 12 a ₁ connected to, for example, word line 28 a, memory cell selection circuitry 110 applies a control signal on word line 28 a and isolation select line 108 a ₁ and clamp transistor line 108 a ₂. In response, isolation transistor 106 a ₁₁ is enabled to couple bit line segment 32 a ₁ to bit line 32 a and clamp transistor 106 a ₁₂ is disabled to release bit line segment 32 a ₁ from the predetermined and/or fixed voltage. The isolation circuit 104 a ₂ is not enabled and, as such, maintains bit line segment 32 a ₂ disconnected from bit line 32 a and maintained at a predetermined and/or fixed voltage. In this regard, isolation transistor 106 a ₂₁ is disabled which de-couples bit line segment 32 a ₂ from bit line 32 a and clamp transistor 106 a ₂₂ is enabled which holds bit line segment 32 a ₂ at a predetermined and/or fixed voltage. In this way, memory cells 12 a ₅-12 b ₈ are isolated from bit line 32 a during the read or write operations and the drain regions of transistors 14 a ₅-14 b ₈ are maintained at a predetermined and/or fixed voltage. Accordingly, such memory cells are less susceptible to voltage/current disturbance on bit line 32 b during the read operation of memory cells 12 a ₁ and the drain regions of transistors 14 a ₅-14 b ₈ do not electrically “float”.

Thus, in operation, when bit line segment 32 a ₂ is isolated from bit line 32 a, any leakage currents that may tend to “charge-up” the bit line segment 32 a ₂ are addressed and/or controlled by enabling clamp transistor 106 a ₂₂, which maintains bit line segment 32 a ₂ at a predetermined and/or fixed voltage. Although this may not present a disturb due to the limited power available, it may be advantageous to eliminate any “charging” of bit line segment 32 a _(x) via the clamp transistor. Notably, the embodiment of FIG. 8A also completes the discharge of bit line segment 32 a _(x) where a PMOS-type transistor is employed as the isolation transistor 106 a.

As noted above, in one embodiment, the present inventions may implement memory cells 12 including N-channel type transistor (see, FIGS. 5A and 6A) or P-channel type transistors (see, FIGS. 5B and 5C). In addition, isolation transistor 106 x _(nm) may be N-channel type transistor(s) (see, FIGS. 8B and 8C) or P-channel type transistors (see, FIGS. 8A and 8D). Moreover, clamp transistors 106 x _(nm+1) may be N-channel type transistor(s) (see, FIGS. 8A and 8C) or P-channel type transistors (see, FIGS. 8B and 8D). All permutations and combinations are intended to fall within the scope of the present inventions.

It may be advantageous to incorporate or provide a timing relationship between the enablement of isolation transistor 106 x _(nm) and the disablement of the associated clamp transistor 106 x _(nm+1) from the predetermined and/or fixed voltage. In this regard, in one embodiment, isolation transistor 106 x _(nm) may be enabled coincident (or substantially coincident) with disabling the associated clamp transistor 106 x _(nm+1). In another embodiment, it may be advantageous to disable the clamp transistor 106 x _(nm+1) prior to enabling the associated isolation transistor 106 x _(nm). In yet another embodiment, it may be advantageous to enable isolation transistor 106 x _(nm) prior to enabling the associated clamp transistor 106 x _(nm+1).

Notably, as mentioned above, the present inventions may include an even number of memory cells 12 associated with a given bit line segment 32 a _(x) or an odd number of memory cells 12 associated with a given bit line segment 32 a _(x). (see, for example, FIG. 9A (wherein three memory cells are associated with each bit line segment) and FIG. 9B (wherein five memory cells are associated with each bit line segment)). Where an odd number of memory cells 12 are connected with a given bit line segment 32 a _(x), the efficiency of memory cell array 102 may be improved and/or enhanced since memory cells 12 of adjacent or neighboring bit line segments 32 a _(x) and 32 a _(x+1) may share a common region (for example, source region) and/or contact area. Moreover, an odd number of memory cells 12 per bit line segment 32 a _(x) may also be advantageous for implementing parity or ECC (error correction code) techniques wherein one of the memory cells coupled to the bit line segment 32 a _(x) may be employed for parity or ECC.

Indeed, while many of the embodiments illustrated herein provide four memory cells connected to an associated bit line segment, any number of memory cells (including 1, 2, 3, 4, 5, 6, 7, 8, 9 10, 11, etc.) may be associated with a given bit line segment. All embodiments and/or features described and illustrated herein may be implemented with an even number of memory cells (for example, 2, 4, 6, 8, 10, 12, etc.) or odd number of memory cells (for example, 1, 3, 5, 7, 9, 11, 13, etc.) being associated with a predetermined bit line segment. For the sake of brevity, such permutations and combinations are not discussed in detail herein. However, all permutations and combinations of odd or even number of memory cells associated with a bit line segment, in conjunction with the embodiments and/or features described and illustrated herein, are intended to fall within the scope of the present inventions.

As mentioned above, the present inventions may be implemented in a logic device having a memory portion and logic portion (see, for example, FIGS. 10A and 10C), or an integrated circuit that is primarily a memory device (see, for example, FIG. 10B). The logic device may be, for example, a processor, controller, field programmable gate array, state machine, and/or a device including same. Indeed, the present inventions may be implemented in any device employing a memory cell array.

Indeed, the present inventions may be implemented in any configuration and/or arrangement of memory cell array 102 and reading and programming circuitry 112. In this regard, integrated circuit device 100 (for example, memory or logic device) may include a plurality of memory cell arrays 12 a-12 x, each having corresponding reading and programming circuitry 112 a-112 x. Moreover, as illustrated in FIG. 11A, adjacent arrays 10 a and 10 b may share reading and programming circuitry 112 b. Alternatively, with reference to FIG. 11B, integrated circuit device 100 may include memory array 102 which is connected to reading and programming circuitry 112 a and 112 b. In this embodiment, memory array 102 may be embedded memory within an integrated circuit device 100 which includes complex and/or extensive logic circuitry (not illustrated). Moreover, integrated circuit 100 may include a plurality of arrays 10 a and 10 b, connected to reading and programming circuitry 112 a-112 d, respectively. The reading and programming circuitry 112 a-112 d may be located or disposed at the edges and in the center of the associated arrays 102 a and 102 b, respectively. (See, for example, FIG. 11C).

Notably, the present inventions may be implemented in conjunction with any memory cell technology, whether now known or later developed. For example, the memory cells may include one or more electrically floating body transistors, one transistor-one capacitor architecture, electrically floating gate transistors, junction field effect transistors (often referred to as JFETs), or any other memory/transistor technology whether now known or later developed. All such memory technologies are intended to fall within the scope of the present inventions.

Further, the present inventions may be implemented in conjunction with any type of memory (including discrete or integrated with logic devices), whether now known or later developed. For example, the memory may be a DRAM, SRAM and/or Flash. All such memories are intended to fall within the scope of the present inventions.

In one embodiment, the memory cells of the memory cell array may include at least one electrically floating body transistor which stores an electrical charge in the electrically floating body region of the transistor. One type of such memory cell is based on, among other things, a floating body effect of semiconductor on insulator (SOI) transistors. (See, for example, (1) U.S. Pat. No. 6,969,662, (2) Okhonin et al., U.S. Patent Application Publication No. 2006/0131650 (“Bipolar Reading Technique for a Memory Cell Having an Electrically Floating Body Transistor”), (3) Okhonin et al., U.S. Patent Application Publication No. 2007/0058427 (“Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same”), (4) U.S. Non-Provisional patent application Ser. No. 11/633,311, Okhonin, filed Dec. 4, 2006 and entitled “Electrically Floating Body Memory Cell and Array, and Method of Operating or Controlling Same”, (5) U.S. Non-Provisional patent application Ser. No. 11/703,429, Okhonin et al., filed on Feb. 7, 2007 and entitled “Multi-Bit Memory Cell Having Electrically Floating Body Transistor, and Method of Programming and Reading Same”, and (6) U.S. Non-Provisional patent application Ser. No. 11/796,935, Okhonin et al., filed on Apr. 30, 2007 and entitled “Semiconductor Memory Cell and Array Using Punch-Though to Program and Read Same”). In this regard, the memory cell may consist of one or more PD and/or FD SOI transistor (or one or more transistors formed on or in bulk material/substrate) having a gate, which is disposed adjacent to the electrically floating body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.

As mentioned above, the memory cells of the memory cell array may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated in detail herein)) may include P-channel and/or N-channel type transistors (including, for example, transistors formed in bulk, PD SOI, FD SOI and/or combinations thereof). Where N-channel type transistors or P-channel type transistors are employed as the memory cells in the memory array(s), suitable write and read voltages are well known to those skilled in the art (and in view of the U.S. patents and U.S. patent applications incorporated herein by reference).

Moreover, the present inventions may be implemented in conjunction with any memory cell array architecture and/or control technique. For example, the present inventions may be employed or implemented in conjunction with one or more of the memory cell arrays and/or techniques for programming, reading, controlling and/or operating a memory cell and memory cell array including, for example, (1) Okhonin et al., U.S. Patent Application Publication No. 2006/0131650 (“Bipolar Reading Technique for a Memory Cell Having an Electrically Floating Body Transistor”), (2) Okhonin et al., U.S. Patent Application Publication No. 2007/0058427 (“Memory Cell and Memory Cell Array Having an Electrically Floating Body Transistor, and Methods of Operating Same”), (3) U.S. Non-Provisional patent application Ser. No. 11/633,311, Okhonin, filed Dec. 4, 2006 and entitled “Electrically Floating Body Memory Cell and Array, and Method of Operating or Controlling Same”, and (4) U.S. Non-Provisional Patent application Ser. No. 11/703,429, Okhonin et al., filed on Feb. 7, 2007 and entitled “Multi-Bit Memory Cell Having Electrically Floating Body Transistor, and Method of Programming and Reading Same”. The entire contents of these U.S. patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference herein in its entirety.

In addition, the memory cells and/or memory cell arrays may be configured and/or controlled using any of the memory cell arrays, architectures and/or control/operation techniques described and illustrated in the following U.S. patent applications:

(1) application Ser. No. 10/450,238, which was filed by Fazan et al. on Jun. 10, 2003 and entitled “Semiconductor Device” (now U.S. Pat. No. 6,969,662);

(2) application Ser. No. 10/487,157, which was filed by Fazan et al. on Feb. 18, 2004 and entitled “Semiconductor Device” (now U.S. Pat. No. 7,061,050);

(3) application Ser. No. 10/829,877, which was filed by Ferrant et al. on Apr. 22, 2004 and entitled “Semiconductor Memory Cell, Array, Architecture and Device, and Method of Operating Same” (now U.S. Pat. No. 7,085,153);

(4) application Ser. No. 10/840,009, which was filed by Ferrant et al. on May 6, 2004 and entitled “Semiconductor Memory Device and Method of Operating Same” (U.S. Patent Application Publication US 2004/0228168);

(5) application Ser. No. 10/941,692, which was filed by Fazan et al. on Sep. 15, 2004 and entitled “Low Power Programming Technique for a One Transistor SOI Memory Device & Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same” (now U.S. Pat. No. 7,184,298); and

(6) application Ser. No. 11/724,552, which was filed by Carman on Mar. 15, 2007 and entitled “Memory Array Having a Programmable Word Length, and Method of Operating Same”.

The entire contents of these six (6) U.S. patent applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein. For the sake of brevity, those discussions will not be repeated; rather those discussions (text and illustrations), including the discussions relating to the memory cell, architecture, layout, structure, are incorporated by reference.

Notably, the present inventions may be fabricated using well known techniques and/or materials. Indeed, any fabrication technique and/or material, whether now known or later developed, may be employed to fabricate the memory cells, transistors and/or memory array(s). For example, the present inventions may employ silicon (whether bulk-type or SOI), germanium, silicon/germanium, gallium arsenide or any other semiconductor material in which transistors may be formed. Indeed, the electrically floating body transistors, memory cells, and/or memory array(s) may employ the techniques described and illustrated in U.S. patent application entitled “Integrated Circuit Device, and Method of Fabricating Same”, which was filed on Jul. 2, 2004, by Fazan, Ser. No. 10/884,481 (U.S. Patent Application Publication US 2005/0017240) and/or U.S. patent application entitled “One Transistor Memory Cell having a Strained Electrically Floating Body Region, and Method of Operating Same”, which was filed on Oct. 12, 2006, and assigned Ser. No. 11/580,169 (U.S. Patent Application Publication US 2007/0085140), by Bassin (hereinafter collectively “Integrated Circuit Device Patent Applications”). The entire contents of the Integrated Circuit Device Patent Applications, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

Further, in one embodiment, an integrated circuit device includes memory section (having a plurality of memory cells, for example, PD or FD SOI memory transistors) and logic section (having, for example, high performance transistors, such as FinFET, multiple gate transistors, and/or non-high performance transistors (for example, single gate transistors that do not possess the performance characteristics of high performance transistors—not illustrated)). Moreover, as noted above, the memory cell and/or memory cell array, as well as the circuitry of the present inventions may be implemented in an integrated circuit device having a memory portion and a logic portion (see, for example, FIGS. 10A and 10C), or an integrated circuit device that is primarily a memory device (see, for example, FIG. 10B). The memory array may include a plurality of memory cells arranged in a plurality of rows and columns wherein each memory cell includes a transistor (whether fabricated in a bulk-type material or SOI material), for example, an electrically floating body transistor. The memory arrays may be comprised of N-channel, P-channel and/or both types of transistors. Indeed, circuitry that is peripheral to the memory array (for example, data sense circuitry (for example, sense amplifiers or comparators), memory cell selection and control circuitry (for example, word line and/or source line drivers), as well as row and column address decoders) may include P-channel and/or N-channel type transistors.

There are many inventions described and illustrated herein. While certain embodiments, features, attributes and advantages of the inventions have been described and illustrated, it should be understood that many others, as well as different and/or similar embodiments, features, attributes and advantages of the present inventions, are apparent from the description and illustrations. As such, the embodiments, features, attributes and advantages of the inventions described and illustrated herein are not exhaustive and it should be understood that such other, similar, as well as different, embodiments, features, attributes and advantages of the present inventions are within the scope of the present inventions.

For example, with reference to FIGS. 12A and 12B, the present inventions may be implemented in conjunction with memory cells 120 which implement any memory cell technology that generates at least two current or voltage values (each current or voltage being representative of, for example, a respective data state) and employs a reference to discriminate such data states. The reference may be a current, voltage and/or time or temporal value (i.e., wherein a data state is determined based on detecting a signal within a given or predetermined period of time (for example, a logic high when a signal is detected with the given or predetermined period of time and a logic low when the signal is not detected with the given or predetermined period of time)).

For example, memory cells 120 may be comprised of electrically floating gate transistors, junction field effect transistors (often referred to as JFETs), or any other memory/transistor technology whether now known or later developed. All such memory technologies are considered to fall within the scope of the present inventions. Indeed, such memory cells may be employed in any of the embodiments described and/or illustrated herein. Indeed, all permutations and combinations of such memory cells with such embodiments and/or features thereof, are intended to fall within the scope of the present inventions. For the sake of brevity, such permutations and combinations are not discussed in detail herein.

Notably, where electrically floating body transistor 14 are employed, electrically floating body transistor 14 may be a symmetrical or non-symmetrical device. Where transistor 14 is symmetrical, the source and drain regions are essentially interchangeable. However, where transistor 14 is a non-symmetrical device, the source or drain regions of transistor 14 have different electrical, physical, doping concentration and/or doping profile characteristics. As such, the source or drain regions of a non-symmetrical device are typically not interchangeable. This notwithstanding, the drain region of the electrically floating N-channel type transistor of the memory cell (whether the source and drain regions are interchangeable or not) is that region of the transistor that is connected to the bit line/sense amplifier.

As mentioned above, the inventions (and embodiments thereof) described and illustrated herein are entirely applicable to N-channel and/or P-channel type transistors. Moreover, while the discussion described and illustrated only source and drain implants, other implants may also be included. For example, implants to modify the operation of memory cells 12, which affect, for example, the power consumption of memory cells 12 as described and illustrated in (1) Fazan et al., U.S. Pat. No. 6,969,662, entitled “Semiconductor Device”, (2) Fazan et al., U.S. Pat. No. 7,061,050 entitled “Semiconductor Device”; and (3) Provisional Application Ser. No. 60/578,631, which was filed on Jun. 10, 2004, and entitled “Asymmetrical Electrically Floating Body Memory Device, and Method of Manufacturing Same”.

Further, as mentioned above, the memory arrays may be comprised of N-channel type transistors, P-channel type transistors and/or both types of transistors, as well as partially depleted and/or fully depleted type transistors. For example, circuitry that is peripheral to the memory array (for example, sense amplifiers or comparators, row and column address decoders, as well as line drivers (not illustrated herein)) may include fully depleted type transistors (whether P-channel and/or N-channel type). Alternatively, such circuitry may include partially depleted type transistors (whether P-channel and/or N-channel type). There are many techniques to integrate both partially depleted and/or fully depleted type transistors on the same substrate (see, for example, U.S. Pat. No. 7,061,050). All such techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.

Notably, memory cell selection circuitry 110 may employ any circuitry and/or technique now known or later developed to select one or more memory cells for reading and/or programming. (See, for example, FIGS. 13A, 13B and 13C). Indeed, all such techniques and circuitry therefor, whether now known or later developed, are intended to fall within the scope of the present inventions.

In addition, reading and programming circuitry 112 may include output pass gates, latches and/or column switch circuitry to facilitate and/or implement read and write operations to memory cells 12. There are many different configurations and techniques (and circuitry therefor) to implement such circuitry. All such configurations and techniques, whether now known or later developed, are intended to fall within the scope of the present inventions.

Further, reference generator circuitry 116 is described in the context of generating, providing and/or supplying a reference current or voltage. The reference current or voltage may be substantially equal to one-half of the summation of the currents in a first reference cell, which has a logic low data state, and a second reference cell, which has a logic high data state. Other circuitry and techniques may be employed to generate the reference currents used by data sense amplifier circuitry to sense, sample and/or determine the data state of a selected memory cell 12. Indeed, all such reference current generation techniques and circuitry therefor, whether now known or later developed, are intended to be within the scope of the present inventions.

For example, the circuitry and techniques described and illustrated in U.S. Pat. No. 6,912,910 (“Reference Current Generator, and Method of Programming, Adjusting and/or Operating Same”, filed May 7, 2004), may be employed to generate an appropriate reference current for data sense amplifier circuitry. The entire contents of U.S. Pat. No. 6,912,910, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

In addition, the present inventions may employ the circuitry and techniques for generating a reference current for data sense amplifier circuitry 102 as described and illustrated in U.S. patent application Ser. No. 11/515,667, which was filed by Bauser on Sep. 5, 2007, and entitled “Method and Circuitry to Generate a Reference Current for Reading a Memory Cell, and Device Implementing Same” (U.S. Patent Application Publication US 2007/0064489). The entire contents of U.S. patent application Ser. No. 11/515,667, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

Further, the present inventions may employ the circuitry and techniques for independently controlling certain parameters (for example, temporal or voltage), for a memory operation (for example, restore, write, refresh), to program or write a predetermined data state into a memory cell (for example, programming or writing data state “1” or “0” into a memory cell) as described and illustrated in U.S. patent application Ser. No. 11/590,147, which was filed by Popoff et al. on Oct. 31, 2006, and entitled “Method and Apparatus for Varying the Programming Duration and/or Voltage of an Electrically Floating Body Transistor, and Memory Cell Array Implementing Same”. For example, the duration of programming/writing/refreshing of a given memory state into a memory cell by data write and sense circuitry may be controlled, adjusted, determined and/or predetermined according to or based on the given memory operation (for example, restore, write, refresh). Likewise, the voltage conditions applied to the memory cell for programming/writing a given memory state into a memory cell by data write and sense circuitry may be controlled and/or adjusted according to the memory operation (for example, restore, write, refresh). The entire contents of U.S. patent application Ser. No. 11/590,147, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

In addition, the present inventions may be employed in conjunction with the circuitry and techniques for generating a voltage, for example, for use during a memory operation (for example, restore, write, refresh) to program or write a data state into a memory cell (for example, programming or writing data state “1” or “0” into a memory cell) as described and illustrated in U.S. Provisional Patent Application Ser. No. 60/932,223, which was filed by Fisch and Bauser on May 30, 2007, and entitled “Integrated Circuit Having Voltage Generation Circuitry for Memory Cell Array, and Method of Operating and/or Controlling Same”. For example, may employ the structure and capacitance of the memory cell array to generate and/or provide one or more voltages used during one or more memory operations. The structure and capacitance of the memory cell array may be modified, changed and/or configured via controlling the number of bit line segments that are connected to the associated bit lines. By connecting one or more bit line segments to a bit line, the capacitance of a predetermined and selected portion the memory cell array can be changed or adjusted. As noted therein, the voltage generation circuitry of the present inventions may be implemented in a local manner (i.e., using two or more bit lines of an array or sub-array) and/or in a more global manner (i.e., using all or substantially all of an array or sub-array) without consuming a significant area of the integrated circuit. Implementing the present inventions in conjunction with the circuitry and techniques of U.S. Patent Application Ser. No. 60/932,223 provides an additional level of controlling the amplitude of the generated voltage. The entire contents of U.S. Patent Application Ser. No. 60/932,223, including, for example, the inventions, features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are hereby incorporated by reference herein.

The embodiments of the inventions described and illustrated above are merely exemplary. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of this disclosure. For example, while many of the embodiments illustrate four memory cells connected to an associated bit line segment, any number of memory cells (including 1, 2, 3, 4, 5, 6, 7, 8, 9 10, 11, etc.) may be associated with a given bit line segment. Thus, it is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. The scope of the inventions is not limited solely to the description above because the description of the above embodiments has been presented for the purposes of illustration and description.

Moreover, there are many inventions described and illustrated herein. The present inventions are neither limited to any single aspect nor embodiment thereof, nor to any combinations and/or permutations of such aspects and/or embodiments. Moreover, each of the aspects of the present inventions, and/or embodiments thereof, may be employed alone or in combination with one or more of the other aspects of the present inventions and/or embodiments thereof. For example, the present inventions may employ an isolation circuit (including, for example, a CMOS type (see FIG. 70) which may or may not include a clamp transistor (see FIG. 8A)) in conjunction with any layout (for example, a mirror type layout (see FIG. 7B)). For the sake of brevity, many of those permutations and combinations are not discussed separately herein.

Further, the above embodiments of the present inventions are merely exemplary embodiments. They are not intended to be exhaustive or to limit the inventions to the precise forms, techniques, materials and/or configurations disclosed. Many modifications and variations are possible in light of the above teaching. It is to be understood that other embodiments may be utilized and operational changes may be made without departing from the scope of the present inventions. As such, the foregoing description of the exemplary embodiments of the inventions has been presented for the purposes of illustration and description. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the inventions not be limited solely to the description above.

For example, although much of the discussion above describes a “default” condition whereby the bit line segments 32 x _(n) are disconnected from the associated bit line 32 x, the “default” condition may include bit line segments 32 x _(n) that are connected to their respective associated bit lines 32 x—for example, during “inactive” memory cycles. As such, during an active cycle, the selected/decoded bit line segment(s) may remain connected to the associated bit line and all unselected or unaddressed segments 32 x _(n) may be isolated from the associated bit lines 32 x via (disabling or enabling) the associated isolation circuits 104. As such, in this embodiment, the bit line segments are connected to their respective associated until the associated isolation circuits are disabled (or enabled depending on the type of isolation circuit employed) thereby disconnecting unselected or unaddressed bit line segments form their associated bit line. Notably, this embodiment may be implemented in any and all of the embodiments discussed above. For the sake of brevity, such discussions will not be repeated.

It should be noted that the term “circuit” may mean, among other things, a single component (for example, electrical/electronic and/or microelectromechanical) or a multiplicity of components (whether in integrated circuit form or otherwise), which are active and/or passive, and which are coupled together to provide or perform a desired function. The term “circuitry” may mean, among other things, a circuit (whether integrated or otherwise), a group of such circuits, one or more processors, one or more state machines, one or more processors implementing software, or a combination of one or more circuits (whether integrated or otherwise), one or more state machines, one or more processors, and/or one or more processors implementing software. The term “data” may mean, among other things, a current or voltage signal(s) whether in an analog or a digital form.

In sum, an isolation circuit disposed between the bit line and a subset of the floating body memory cells may alleviate, minimize, manage and/or control disturbance on the bit line of other memory cells. The use of an isolation circuit in this manner provides a plurality of bit line segments, associated with a given bit line, which are selectively and responsively coupled to the associated bit line via the isolation circuit. This architecture may provide the advantage of allowing longer bit lines which improves array utilization. Indeed, the segmented bit line architecture of the present inventions may enhance the burst read and write operations where the memory cells of an associated bit line segment may be read or written in a burst read or burst write manner via, among other things, enabling the associated isolation circuit. 

1. An integrated circuit device comprising: a memory cell array comprising: a plurality of bit lines; a plurality of bit line segments, wherein at least two bit line segments are associated with each of the plurality of bit lines, and wherein each of the plurality of bit line segments is configured to be selectively and responsively coupled to or decoupled from an associated bit line; a plurality of word lines; and a plurality of memory cells, wherein each of the plurality of memory cells stores at least two data states and comprises a transistor, wherein the transistor comprises: a first region coupled to an associated bit line segment; a second region; a body region disposed between the first region and the second region; and a gate coupled to an associated word line; wherein: (i) a first group of memory cells is coupled to a first bit line via a first bit line segment; and (ii) a second group of memory cells is coupled to the first bit line via a second bit line segment; and a plurality of isolation circuits, wherein each of the plurality of isolation circuits is associated with a bit line segment and is disposed between the associated bit line segment and an associated bit line, and comprises a transistor comprising: (i) a first region coupled to the associated bit line; (ii) a second region coupled to the associated bit line segment; (iii) a body region disposed between the first region and the second region; and (iv) a gate configured to receive a control signal, wherein: (i) a first isolation circuit is disposed between the first bit line segment and the first bit line; and(ii) a second isolation circuit is disposed between the second bit line segment and the first bit line.
 2. The integrated circuit device of claim 1, wherein the first group of memory cells comprises an odd number of memory cells and the second group of memory cells comprises an odd number of memory cells.
 3. The integrated circuit device of claim 1, wherein the plurality of memory cells further comprises a third group of memory cells coupled to a second bit line via a third bit line segment, and a fourth group of memory cells coupled to the second bit line via a fourth bit line segment.
 4. The integrated circuit device of claim 3, wherein the third group of memory cells comprises an odd number of memory cells and the fourth group of memory cells comprises an odd number of memory cells.
 5. The integrated circuit device of claim 1, wherein the plurality of isolation circuits further comprises a third isolation circuit that is disposed between the third bit line segment and the second bit line, and a fourth isolation circuit that is disposed between the fourth bit line segment and the second bit line.
 6. The integrated circuit device of claim 1, wherein the transistor of the first isolation circuit and the transistor of the second isolation circuit share a first region.
 7. The integrated circuit device of claim 1, wherein each of the plurality of isolation circuits further comprises a second transistor comprising: (i) a first region coupled to the associated bit line segment; (ii) a second region coupled to a predetermined voltage; (iii) a body region disposed between the first region and the second region; and (iv) a gate configured to receive a control signal.
 8. The integrated circuit device of claim 7, wherein: (i) the first transistor is a P-type or an N-type transistor; and (ii) the second transistor is a P-type or an N-type transistor.
 9. The integrated circuit device of claim 1, wherein each of the plurality of isolation circuits comprises a plurality of transistors comprising the first transistor and a second transistor, wherein the first and second transistors are arranged in a CMOS configuration.
 10. The integrated circuit device of claim 1, wherein at least one memory cell of the first group of memory cells shares a common region with at least one memory cell of the second group of memory cells.
 11. The integrated circuit device of claim 1, further comprising data sense circuitry coupled to the first bit line to sense data states stored in selected memory cells of the first group of memory cells and the second group of memory cells.
 12. A memory device comprising: a plurality of floating body memory cells, wherein each of the plurality of floating body memory cells comprises a transistor and is configured to store at least two data states, wherein the transistor of each of the plurality of floating body memory cells comprises: a source region; a drain region; a body region configured to store charge carriers, wherein the amount of charge carriers stored in the body region is representative of the data state of each of the plurality of floating body memory cells; and a gate; a plurality of bit lines; a plurality of bit line segments, wherein each of the plurality of bit line segments is configured to be selectively and responsively coupled to or decoupled from an associated bit line via an isolation circuit; and a plurality of word lines coupled to the gate of each of the plurality of floating body memory cells.
 13. The memory device of claim 12, wherein the plurality of floating body memory cells comprises a first group of floating body memory cells coupled to a first bit line via a first bit line segment and a second group of floating body memory cells coupled to the first bit line via a second bit line segment.
 14. The memory device of claim 13, wherein the first group of floating body memory cells comprises forming an odd number of floating body memory cells and the second group of floating memory cells comprises forming an odd number of floating body memory cells.
 15. The memory device of claim 13, wherein at least one floating body memory cell of the first group of floating body memory cells is formed to share a common region with at least one floating body memory cell of the second group of floating body memory cells.
 16. The memory device of claim 12, wherein the plurality of floating body memory cells further comprises a third group of floating body memory cells coupled to a second bit line via a third bit line segment and a fourth group of floating body memory cells coupled to the second bit line via a fourth bit line segment.
 17. The memory device of claim 16, wherein the third group of memory cells comprises an odd number of floating body memory cells and the fourth group of memory cells comprises an odd number of floating body memory cells.
 18. The memory device of claim 12, wherein the isolation circuit is disposed between an associated bit line segment and the associated bit line.
 19. The memory device of claim 18, wherein the isolation circuit comprises a transistor comprising: (i) a first region coupled to the associated bit line; (ii) a second region coupled to the associated bit line segment; (iii) an electrically floating body region disposed between the first region and the second region; and (iv) a gate configured to receive a control signal.
 20. The memory device of claim 19, wherein the plurality of isolation circuits further comprises a second transistor comprising: (i) a first region coupled to the associated bit line segment; (ii) a second region coupled to a predetermined voltage; (iii) an electrically floating body region disposed between the first region and the second region; and (iv) a gate configured to receive a control signal.
 21. The memory device of claim 20, wherein: (i) the first transistor is a P-type or an N-type transistor; and (ii) the second transistor is a P-type or an N-type transistor.
 22. The memory device of claim 12, wherein the isolation circuit comprises a plurality of transistors comprising the first transistor and a second transistor, wherein the first and second transistors are arranged in a CMOS configuration. 